The present invention relates to self-aligned silicidation of a semiconductor device, and more particularly, but not exclusively relates to a technique to form a silicide layer on the gate of a field effect transistor by a self-aligned process independent of the self-aligned formation of a silicide layer on the source and drain of the transistor.
Self-aligned silicidation involves a blanket deposition of a metal on a silicon substrate with silicon patterns defined by field oxide isolation, which is then heated to induce metal-silicon reactions and form a low resistance silicide. Silicides are typically used to provide low resistance electrical interconnections for semiconductor devices of an Integrated Circuit (IC).
Advances in integrated circuit speed and device density frequently involve the shrinking of various semiconductor device features. For field effect transistors, feature shrinkage frequently entails not only narrowing of the transistor gate, but also reducing junction depth in the active source/drain areas. Generally, to avoid junction leakage of such transistors, silicide thickness at the active source and drain silicon areas also needs to be reduced. As a consequence, the silicide thickness for a polysilicon gate, typically formed along with the source/drain silicide, would also be reduced. However, scaling down of the silicide thickness poses a major challenge for deep submicron technology (e.g. gate lengths less than or equal to about 0.35 .mu.m) because the accompanying increase in sheet resistance of thinner silicides greatly aggravates narrow linewidth effects experienced with polysilicon gates of decreasing size. Thus, there is a demand for a method to provide a thicker silicide layer for a polysilicon gate, while not increasing the silicide thickness in the active source and drain regions.
Another challenge in reducing device dimensions is the cost-effective implementation of antireflective coatings (ARCs) to improve photolithography definition. It is attractive to employ the inorganic bottom antireflective coating (BARC) material SiON on the polysilicon transistor gate because of the ease with which it may be integrated into a photolithography process. The use SiON as a BARC; however, poses challenges to subsequent processes, such as self-aligned silicidation because the BARC layer must be removed from the polysilicon surface so that the metal can react to form the silicide. The BARC removal by wet or dry etching proves complicated, because it is generally accompanied by additional oxide loss in the field isolation structure (such as a shallow isolation trench) or silicon loss in active source/drain area. Such losses may lead to device failure. Thus, a need exists for a technique to remove BARC coatings from polysilicon gates to perform silicidation without damaging other semiconductor device regions.
The present invention satisfies these demands and needs, and provides other significant advantages.